A general FIR filtering operation can be represented by the following equation: ##EQU1## in which each term x(n-m) represents an input signal component applied to a digital filter, each term a(m) is a filter coefficient representing the characteristics of the digital filter, and y(n) is the resulting output signal provided by the digital filter. FIG. 1 shows a prior art FIR digital filter 10 in transposed form implementing the general FIR filtering operation of equation (1). Filter 10 includes M-number of identical cells 12.sub.0, 12.sub.1, . . . , 12.sub.M-1 connected to an input 14. A subscript lower case "m" is used to refer generally to one of cells 12.sub.0, 12.sub.1, . . . , 12.sub.M-1 or its components.
Each cell 12.sub.m includes a multiplier 16.sub.m for multiplying an input signal component x(n-m) by a corresponding filter coefficient a(m) stored in a register 18.sub.m. An adder 20.sub.m in each cell 12.sub.m adds the product provided by multiplier 16.sub.m to a sum of products provided by adder 20.sub.m-1 of cell 12.sub.m-1. A register 22.sub.m in each cell 12.sub.m provides a delay after adder 20.sub.m to synchronize the application of signals to each successive adder 20.sub.m+1. Digital filter 10 is referred to as transposed due to registers 22.sub.m being positioned between 20.sub.m adders.
The transposed form of digital filter 10 is advantageous because each cell 12.sub.m has a regular configuration that allows multiple cells to be connected together or "cascaded" to increase the filter length and modified to accommodate multiple channels. As a result, digital filter 10 is well suited for implementation in an application-specific integrated circuit (ASIC). A disadvantage of digital filter 10, however, is that it employs twice the number multipliers 16.sub.m, which are relatively large, complex components, as are required by a symmetric filter as shown in FIG. 2.
FIG. 2 shows a prior art FIR digital filter 26 in symmetric form implementing a linear-phase FIR filtering operation. A linear-phase filter has symmetric filter coefficients in which a(m)=a(M-1-m) such as, for example a(0)=a(M-1). To process the M-number of input signal components x(n-m) of equation (1), filter 26 includes (M/2)-number of adders 28.sub.0, 28.sub.1, . . . , 28.sub.M/2-1 connected to an input 30 to receive pairs of symmetric input signal components x(0) and x(M-1), x(1) and x(M-2), . . . , x(M/2) and x(M/2-1), respectively. Delay registers 32.sub.0, 32.sub.1, . . . , and 32.sub.M-1 are connected to input 36 and coordinate the application of the input signal components to adders 28.sub.0, 28.sub.1, . . . , 28.sub.M/2-1. Multipliers 38.sub.0, 38.sub.1, . . . , 38.sub.M/2-1 receive the sums provided by respective adders 28.sub.0, 28.sub.1, . . . , 28.sub.M/2-1 and multiply the sums by symmetric filter coefficients a(0), a(1), . .., a(M/2-1) stored in registers 40.sub.0, 40.sub.1, . . . , 40.sub.M/2-1, respectively. The product formed by each multiplier 38.sub.m is delivered to a chain of adders 42 to form the output of digital filter 26.
An advantage of the symmetric configuration of digital filter 26 is that the number of multipliers 38.sub.m is reduced approximately by one-half. Digital filter 26 is disadvantageous, however, because it is not well suited for ASIC implementation due to the irregularity of its direct form cell shape, and because it is not suitable for decimation.
FIG. 3 shows a prior art FIR digital filter 48 that incorporates decimation and is sometimes called a "decimator." Digital filter 48 is generally similar to filter 10 of FIG. 1, except that the former includes only M/L-number of identical cells 50.sub.0, 50.sub.1, . . . , 50.sub.M/L connected to an input 52 to process M-number of input signal components. Each cell 50.sub.m includes a multiplier 54.sub.m for multiplying L-number of input signal components by corresponding filter coefficients a(m), a(m+l), . . . , a(m+L) stored in a register 56.sub.m. An adder 58.sub.m cooperates with a delay register 60.sub.m and a 2-to-1 multiplexer 62.sub.m to add or accumulate the products of the input signal components and corresponding filter coefficients provided by multiplier 54.sub.m. After accumulating L-number of such products, a forward control signal is applied to a forward control input 66.sub.m of multiplexer 62.sub.m to pass the accumulated value to multiplexer 62.sub.m-1 and adder 58.sub.m-1 of next successive cell 50.sub.m-1. Although decimation permits a reduction in the number of cells, digital filter 48 suffers from the same disadvantages discussed with respect to transposed digital filter 10.
Prior art digital filters 10, 26, and 48 typically use fixed-point processing of the input signal components and filter coefficients, which processing limits accuracy due to truncation or round-off error. More specifically, fixed-point processing represents a number by a fixed number of bits having a fixed exponent value (fixed with respect to a decimal). If a number is too small to be wholly represented within those fixed bits, as is often the case with filter coefficients, then to the extent the number is not utilized, error is induced. Furthermore, it is possible in filters of long length that a coefficient is so small that it is not represented at all in the fixed point register, thus inducing significant error.